Traditional tristate drivers for bi-directional buses drive bus lines HIGH or LOW only after the clock and data signals become valid. Presetting the bus to voltages intermediate to HIGH and LOW during a preset cycle before valid data is to be asserted on the bus can improve performance, for when the data is valid, the driver need not drive the bus through the entire voltage range. Ideally, if the driver interfaces with a symmetric receiver, i.e., a receiver with a trip point half way between ground and the supply voltage, then the bus voltage should be preset to half the supply voltage during the preset cycle.
Various methods exist for presetting bus lines by using transistors other than the pullup or pulldown transistors in the drivers. However, these additional transistors need to be sized appropriately to draw enough current fast enough to charge or discharge the bus during a preset cycle. Therefore, it would be advantageous to preset the bus lines during the preset cycle without the need for additional transistors sized to drive the bus, and to do so without DC power being wasted during the preset cycle.